1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of selectively processing wafer edge regions to increase wafer uniformity, and a system for accomplishing same.
2. Description of the Related Art
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting wafer. By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting wafer 11 comprised of doped-silicon. The wafer 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the wafer 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown).
In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes, along with various ion implant and heating processes, are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the wafer. These conductive interconnections allow electrical signals to propagate between the transistors formed above the wafer.
As shown in FIG. 2, a plurality of die 26 are typically formed above the wafer 11. The die 26 define the area of the wafer 11 where production integrated circuit devices, e.g., microprocessors, ASICs, memory devices, will be formed. The size, shape and number of die 26 per wafer 11 depend upon the type of device under construction. For example, several hundred die 26 may be formed above an 8-inch diameter wafer 11. The wafer 11 may also have an alignment notch 17 that is used to provide relatively rough alignment of the wafer 11 prior to performing certain processes, e.g., an alignment process prior to performing an exposure process in a stepper tool.
During the course of manufacturing integrated circuit devices, the thickness of a process layer (not shown) formed above the wafer 11 may vary across the surface of the wafer. That is, the process layer may exhibit a center-to-edge profile in which the layer is thicker at the edge of the wafer than at the center of the wafer, or vice versa. Such across-wafer thickness variations may be caused by, or be the result of, various manufacturing operations. For example, many process layers, e.g., inter-level dielectric layers, are subjected to one or more chemical mechanical polishing (CMP) processes in an attempt to produce an approximately planar upper surface on the layer. Unfortunately, due to a variety of reasons, the chemical mechanical polishing process may result in the process layer being thicker toward the edge of the wafer 11 than at the approximate center of the wafer 11. That is, the surface topography of the process layer after the chemical mechanical polishing process is performed may be somewhat concave. Chemical mechanical polishing processes that result in process layers having such concave surface topography are sometimes referred to as center-fast or edge-slow polishing processes due to the extra thickness of the process layer toward the edge of the wafer 11.
Deposition processes may also produce process layers that exhibit similar thickness variations across the center of a wafer. For example, deposition processes, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), etc., may produce process layers that are thicker at the edge of the wafer than at the center of the wafer. Such variations may be caused by a variety of factors, e.g., cleanliness of the deposition tool, process gas composition, temperature variation within the deposition tool, etc.
Unfortunately, such thickness variations may be problematic with respect to subsequent manufacturing operations to be performed after the process layer is formed. For example, if a process layer, as deposited, is thicker at the edge of the wafer 11 than at the center of the wafer 11, a subsequent chemical mechanical polishing process may have to be varied in an effort to reduce the excess thickness of the layer near the edge of the wafer 11. That is, the chemical mechanical polishing process may be varied such that it removes more material near the edge region of the wafer than at the center of the wafer. Such a polishing process is sometimes referred to as an edge-fast or center-slow polishing process. This compensating chemical mechanical polishing process is performed until such time as the excess thickness of the process layer is removed.
However, in modern semiconductor manufacturing, most, if not all, wafers have non-production areas, i.e., areas where production die cannot be formed due to a variety of reasons, e.g., unavailability of plot space. Unfortunately, the portions of the process layer formed above these non-production areas are subject to the same type of processing performed on the portions of the process layer formed above production areas of the wafer 11, e.g., the plurality of die 26. Accordingly, such compensatory processes may be longer in duration than necessary as a result of removing the excess thickness of the portions of the process layer formed above the non-production areas.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
In general, the present invention is directed to a method of selectively processing wafer edge regions to increase wafer uniformity, and a system for accomplishing same. In one illustrative embodiment, the method disclosed herein comprises providing a wafer comprised of at least one non-production area, forming a process layer above the wafer, forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and performing a process operation on the exposed portion of the process layer formed above the at least one non-production area.
In another aspect, the present invention is directed to a system that comprises a controller for identifying at least one non-production area of a wafer, a photolithography tool for forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and an etch tool for performing an etching process on the exposed portion of the process layer formed above the at least one non-production area.